MMX PROCESSOR ARCHITECTURE DESIGN

The classic Pentium consists of two 64-bit register sets

    1. integer register
    2. floating point register

The MMX Pentium consists of three 64-bit register sets

    1. integer register
    2. floating point register
    3. MMX register

The MMX register consists of 57 new instructions.

The MMX CPU also adds more L1 (on chip) cache.

    1. 486 L1 cache = 8K
    2. Pentium and Pentium Pro L1 cache = 16K
    3. MMX technology chips (standard and overdrive) L1 cache = 32K

MMX register functions

    1. loads multiple data with simultaneous processing
    2. Works on SIMD principle (Single Instruction Multiple Data)
      classic example:
      Color images are processed first red, then green, then blue to display an image.

MMX example

MMX processes all colors and more at one time without a video accelerator card.

MMX features

    1. MMX doubles on chip L1 cache (total of 32K)
    2. MMX uses branch prediction algorithm and logic similar to the Pentium PRO
    3. MMX is available in 166MHz and higher only (except overdrive 133 processor)

Pentium II features

    1. integrated MMX technology starting at 223MHz with standard 32K L1 cache 512K L2 cache
    2. SEC (single edge contact) Slot 1 configuration
    3. Dynamic execution
    4. Speculative execution of code

 CPU Technical Properties

Pentium Pro and Pentium II MMX are both 32-bit processors with 64-bit data path.

Both have 7.5 million transistors in the microprocessor (not including cache).

 

Differences between Pentium Pro and Pentium II MMX processors

    1. both have a microprocessor, 32K L1 cache, and an L2 cache
    2. The Pentium Pro has up to 1MB L2 cache linked to the microprocessor at full speed
      If the CPU is 200MHz the L2 cache is 200MHz
    3. The Pentium II MMX has 512K L2 cache linked to the microprocessor at half speed

If the CPU speed is 300MHz the L2 cache is 150MHz


Intel thinks the half speed cache is OK because of its increased size, but this is not so.
All of your repetitive processing power comes from the combined cache size and speed.


Bus bandwidth limitations
486 and Pentium are limited:

(CPU)

(Main Memory) and (L2 Cache)

(PCI Bus)

(Disk Access) and (Graphics Display)

The L2 cache is limited to the speed of the system bus.
The bus allows one access at a time.
The main memory and L2 cache memory are sharing bandwidth to the CPU.
The PCI bus is waiting on response from main memory.

Pentium Pro and Pentium II MMX have a dual independent bus:

(CPU) and (L2 Cache)

(Main Memory) and (PCI Bus)

(Disk Access) and (Graphics Display)

The dedicated L2 cache is closely coupled to the CPU for maximum speed.
Cache speed scales with core CPU frequency
PCI Bus is independent of the main memory.

Three areas of processor performance
1) Integer performance – Necessary for database and spreadsheet applications
2) Floating point performance – required for CAD, graphics, and 3D rendering
3) Multimedia performance – Accelerated high resolution graphics, video, and PC imaging


Comparing
Classic Pentium 200 vs. Pentium II 266

Double the performance

The desktop roadmap is going to be all MMX

The server environment is developed around multi processor execution

Pentium Pro was designed to work in 1 to 4 way multi processor implementation

Pentium II MMX was design to work in 1 to 2 way dual processor environments

Pentium Pro 1MB CPU was designed to be the workhorse of the server industry

The mobile group is gearing toward all MMX technology, but currently the Pentium II CPU is too large to incorporate into today’s ever decreasing notebook sizes.


Key Repeatables
MMX technology enhances a users audio, video, and communications experiences.
The Pentium II incorporates dynamic execution and MMX technology all in an SEC cartridge.